The present invention relates generally to semiconductor devices and specifically to transistors having stress induced channel regions and methods of making transistors having stress induced channel regions.
Advances in transistor designs have discovered that creating a stress in the channel region of a transistor, which is located under the gate and in between the source and drain, results in a transistor having advantages electrical properties. Various methods have been used to create the stress in the channel region of the transistor including using silicon-germanium as the source and drain materials for PMOS. Other examples of materials used to create stress in the channel region include using source and drain material made of silicon and carbon in NMOS.
Although doping silicon with germanium or carbon does improve some of the electrical properties of the transistor, there are problems with using these dopants. For example, using germanium to create silicon-germanium (Si—Ge) source and drain regions causes stress related problems. For example, the problem with Si—Ge is that at high Ge concentrations>30% Si—Ge tends to relax under thermal processes. Using carbon to create silicon-carbon (Si—C) source and drain regions creates meta-stable transistors wherein the carbon migrates out. The problem is that substitutional carbon is lost during integration, especially for highly N-type doped Si—C film. The reason for this loss is that when more than 1% substitutional C is placed in a silicon lattice, the carbon is in meta-stable state. Since using more than 1% substitutional C in the silicon lattice structure is generally preferred to have advantages, doping the source and drain regions with carbon is less than ideal. The problem with substitutional carbon migrating out becomes much worse when the transistor is exposed to high temperatures such as annealing temperatures. Since Si—C is meta-stable at higher temperatures, a transistor using Si—C might not survive the post thermal treatment required by device integration.
Another problem with using Si—C as the material for the source and drain of a transistor is that Si—C requires a reasonable high selective growth rate which is generally achieved by using higher processing temperatures. However, since carbon migrates at high temperatures because of the meta-stable substitutional C in the silicon lattice that contains Si—C, a transistor that is built using Si—C must be processed at low process temperatures of less than 600° C. Therefore, using Si—C presents problems because higher processing temperatures are desired to make better processes but the Si—C is unstable at the higher processing temperatures.
Therefore, what is needed is a system and method for creating a stress in the channel region of a transistor that is compatible with the high temperature annealing processes that the transistor undergoes during its manufacture.